The present disclosure herein relates to a data processing system, and more particularly, to an asynchronous upsizing commonly having an async bridge function in mobile systems such as smart phones and navigation devices.
In mobile systems such as smart phones, personal navigation devices, portable Internet devices, portable broadcasting devices, or multimedia devices, high performance mobile application processors operating at a high frequency are being used on a System on Chip (hereinafter, referred to as “SoC”) to support various applications.
Since the mobile application processors take charge of arithmetic operation and program command execution, the mobile application processors are essential elements that affect performance of a mobile SoC. The mobile application processors may include an on-chip secondary cache, called as an L2 (level 2) cache, to enable integration of various functions such as wireless communication, personal navigation, camera, portable gaming, portable music/video player, mobile TV, and Personal Digital Assistant (PDA). The addition of the L2 cache is a known method for increasing the performance of a mobile system when heavy memory traffic occurs due to a processor.
For effective design of the SoC, the selection of a bus system for mutual communication is one choice between a plurality of pre-designed Intellectual Properties (IPs) (purchased peripheral functional blocks) to be integrated on one chip. A typical example of known bus systems is an AMBA 3.0 Advanced eXetensible Interface (AXI) bus system based on AMBA protocol from Advanced RISC Machine (ARM) Inc.
Because of constraints such as development time and manpower, peripheral functional blocks such as Direct Memory Access Controller (DMAC), Universal Serial Bus (USB), Peripheral Component Interconnection (PCI), Static Memory Controller (SMC), and Smart Card Interface (SCI) that are parts of SoC may be purchased as IPs from the outside vendors. The purchased peripheral functional block IPs are integrated on a chip along with Central Processing Unit (CPU) and data processing functional blocks to constitute the SoC.
With an increase in consumer demand for high performance of mobile application processors, the operating frequency of a CPU and a cache controller in a SoC has reached several gigahertz (GHz). By contrast, the frequency of the bus system has not increased to several GHz. Instead, a data bus width wider than that of the CPU is employed to reduce the data transmission rate (frequency). For example, when the data bus width of a CPU having an operating frequency of about 1 GHz is 64-bit, the operating frequency of the bus system may be designed to have an operating frequency of about 200 MHz and a data bus width of about 128-bit.
Accordingly, in order to adjust the data transmission rate, an 64-bit data to 128-bit data upsizer circuit may be provided between a Central Processing Unit (CPU connectable to a cache controller and having a 64-bit data bus width and a 1 GHz operating frequency) and a bus system having a 128-bit data bus width and a 200 MHz operating frequency (transmission rate).
An asynchronous bridge (“async bridge”) is widely used due to an increase of the size of a SoC design, and a 128-bit AXI bus has been introduced due to an increase of the bandwidth demand and thus the performance of the upsizer and the async bridge is recognized as an important factor. Both an async bridge and an upsizer are needed for the display IP path. Analysis of traffic patterns of such display IPs often results in successive burst read requests.
When read requests are successively shown in a display subsystem in which the display IPs are gathered, a ‘read ready’ signal may not be maintained high due to a bandwidth difference by the async bridge and the upsizer. In such a case, the operation of a memory controller may be stopped which affects the performance of the whole system. Accordingly, in order to minimize the degradation of performance, the ‘read ready’ signal provided to the memory controller has to be maintained high. In this case, since both of the async bridge and the upsizer require buffers, a gate (e.g., transistor) count overhead may be increased.
Also, when compaction is performed on a write address channel and a write data channel to increase bus utility in the case of a burst write, more efficient compaction schemes are required. For example, when the async bridge and the upsizer are individual and separated from each other, the efficiency of the channel compaction may be reduced, resulting in degradation of the latency and the bus utility.
Therefore, more efficient channel compaction technologies are required to reduce the gate count overhead in an async bridge and an upsizer applicable to a mobile system.